1. Technical Field
The present invention relates to a semiconductor wafer, a field-effect transistor, a method of producing a semiconductor wafer, and a method of producing a field-effect transistor. The present patent application is related to a research sponsored by 2009, NEDO “Nanoelectronics Semiconductor New Material/New Structure Nanoelectronic Device Technological Development, Research and Development of Group III-V Semiconductor Channel Transistor Technology on Silicon Platform” and filed under the Industrial Technology Enhancement Act, Article 19.
2. Related Art
A Group III-V MISFET (metal-insulator-semiconductor field-effect transistor) utilizing a Group III-V compound semiconductor layer as a channel material exhibits a high electron mobility and is expected to serve as a switching device suitable for high-frequency and high-power operation. A Group III-V MISFET is considered to be a promising alternative of a Si CMOSFET (complementary metal-oxide-semiconductor field-effect transistor) utilizing silicon for a channel material. When Group III-V MISFETs are used to constitute complementary elements to produce an LSI (Large Scale Integration), it is preferable to form the Group III-V MISFETs on a silicon wafer so as to use the existing production equipment and the existing production process.
Non-Patent Documents 1 and 2 disclose a MISFET utilizing a Group III-V compound semiconductor material for the channel layer. Non-Patent Document 3 discloses that the energy level existing at the interface between the semiconductor and the insulator (herein, referred to as “the interface state”) may be effectively reduced by, for example, treating the compound semiconductor surface with an ammonia sulfide solution.
Non-Patent Document 1: Ren, F. et al. Demonstration of enhancement-mode p- and n-channel GaAs MOSFETs with Ga2O3(Gd2O3) As gate oxide. Solid State Electron. 41, 1751-1753 (1997).
Non-Patent Document 2: Chin, H. C. et al. Silane-ammonia surface passivation for gallium arsenide surface-channel n-MOSFETs. IEEE Electron Device Lett. 30, 110-112 (2009).
Non-Patent Document 3: S. Arabasz, et al., Vac. Vol. 80 (2006), Page 888
To produce a Group III-V MISFET on a silicon wafer, a Group III-V compound semiconductor layer needs to be formed on the silicon wafer. However, there is a large difference in lattice constant between the Group III-V compound semiconductor layer and the silicon wafer. Therefore, it is difficult to form a high-quality Group III-V compound semiconductor layer by epitaxial growth.
In response, a Group III-V compound semiconductor layer may be formed on a silicon wafer using a direct wafer bonding (DWB) method, which is known as an optical device integration technology, in other words, by directly bonding wafers to each other. When the DWB method is employed, however, the Group III-V compound semiconductor layer may experience damages, for example, generation of crystal defects after the bonding process. When the damage is too serious, the Group III-V compound semiconductor layer can be difficult to be used as a channel material of the MISFET. In particular, a Group III-V compound semiconductor layer is more obviously damaged in the case of an ultra-thin-body MISFET having an extremely thin Group III-V compound semiconductor layer.
There is also a strong demand for further improvement of the performance of Group III-V MISFETs. In particular, it is highly requested to achieve high carrier mobility. An interface state exists at the interface between a channel layer and a gate insulator layer. If carriers are trapped in the interface state, the carrier mobility is degraded due to coulomb scattering and other reasons. Accordingly, it is desirable to further lower the interface state. Furthermore, irrespective of a certain high interface state density at a MIS interface, it is desirable to further enhance the performance of FETs by taking measures to minimize the influence of the interface state existing at the MIS interface.
An objective of the present invention is to provide a Group III-V MISFET having a high carrier mobility by reducing the damage to be experienced by a Group III-V compound semiconductor layer when the DWB method is employed and the Group III-V compound semiconductor layer is bonded to a wafer and mitigating the influences of the experienced damage and the interface state.